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  • Frederico Pratas, Bruno Jacinto, Carlos Moreira and Marcelino Santos

    An analog-to-digital (A/D) conversion technique suitable to be used with DC-DC converters with digital control is proposed. A fully asynchronous modular tracking analog-to-digital converter (ADC) is described.

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  • Abílio Parreira, Floriberto Lima and Marcelino Bicho dos Santos

    This paper presents a solution for controlling integrated DC-DC converters with switching frequency above 20 MHz. The increase of the switching frequency is a trend biased by output filter volume restrictions and integration demand. The control of DC-DC converters operating at high frequency presents an opportunity to speed up the converter response time but also a challenge specially to limit the sensitivity to process and operating conditions for the mixed signal circuits involved. The solution presented in this work relies on separating the duty-cycle into three parts: an OP load-free value that depends only on the input and output voltages, a transient fast correction contribution, and an accurate compensation for the IR drop that depends on the load current. The duty-cycle is obtained with these contributions in two digitally controlled delays. The OP portion of the delay has a compensation of PVT variations and the fast transient part of the duty-cycle uses a non-linear sliding mode control solution.

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  • Tiago Manuel Oliveira Henriques Moita, Carlos Beltran Almeida and Marcelino Bicho dos Santos

    This paper presents a new methodology that establishes a bridge between design and test of mixed-signal integrated circuits. The information present in the schematics, used for design validation (testbenches) during the design phase, is usually not reused in the characterization test of the silicon. Moreover, the feedback that designers can obtain from the lab is presently limited since designers are frequently not familiar with the configuration of the test setup and the visualization options available for the test results. The aim of this work is to allow the characterization test of integrated circuits through the use of interfaces that are familiar to designers: the schematics used for design validation and the visualization tools they use for their simulation results. This approach allows the use of silicon as it was an additional simulator now available for the designer, thus closing the design loop, at the same time that allows a reduction of cost and time devoted to the characterization test.

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  • Nuno Guerreiro, Marcelino Santos and Paulo Teixeira

    Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive
    in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study — a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.

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  • Jorge Esteves João Pereira, Júlio Paisana and Marcelino Santos

    In this paper, a low power, output-capacitor-free, low-dropout regulator (LDO) is proposed with a new dynamic biased, multiloop feedback strategy. Initially, a theoretical macromodel is presented based on the analogy between the capless LDO and the mechanical non-linear harmonic oscillator, enabling to shed new light on the non-linear amplification, dynamic and adaptive biasing techniques used in the multiloop feedback LDO control in the large signal context. To implement some of the unexplored abilities of this model the new capless LDO topology is proposed. The output class AB stage of the error amplifier and the non-linear derivative current amplifier of the LDO feedback loop ensure dynamical extended close-loop bandwidth gain and dynamical damping enhancement for fast load and line LDO transients. Using the new dynamic biasing of the derivative loop, an improvement is obtained in the derivative sensing of the fast output voltage variations, enabling a significant enhancement in the transient response of the capless LDO. The proposed LDO, designed for a maximum current of 50 mA in UMC RF 1P8M 0.13 μm, requires a quiescent current of only 4.1 μA and presents excellent transient response when compared to the state-of-the-art.

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  • Valter António Louzeiro Sádio, Fabian Rein, Christian Münker and Marcelino Bicho dos Santos

    This paper presents an accurate new model for the losses related with charge/discharge process in switched capacitor (SC) DC–DC converters, named from now on inherent losses, considering especially the full integration of the converter. The model was developed for a voltage doubler and it is based on the differential equations of the circuit. It is considered that the output capacitor (C OUT) has dimensions comparable to the flying capacitors (C FLY). That leads to a more complex, but also more realistic, model of the circuit, especially for fully integrated converters. Usually, in SC DC–DC converters with external capacitors, C OUT C FLY, and a simple RC first order model can be used, but for fully integrated SC DC–DC converters, other techniques are applied to lower the voltage ripple instead of just using a large C OUT. Simulations of a voltage doubler were performed to be used as reference and to validate the model that is also compared with other models from recent publications. The results showed that this model is more accurate in calculating the power losses of the voltage doubler across a wide range of C FLY and C OUT values, being a model with small complexity. Compared to simulation results, the proposed model presents a maximum relative error around 0.13%, while previous models present maximum errors that are, at least, 6%. This modeling is particularly important because it may be used in the optimization of the SC DC–DC converter taking into account the specifications and area limit, if the dynamic losses associated to the parasitic capacitances in the circuit are considered.

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  • Ricardo S. Oliveira, Jorge Filipe Leal Costa Semião and Isabel Maria Silva Nobre Parreira Cacho Teixeira, Marcelino Bicho dos Santos and João Paulo Cacho Teixeira, 

    Electronic design of high-performance digital systems in nano-scale CMOS technologies under Process, power supply Voltage, Temperature and Aging (PVTA) variations is a challenging task. Such variations induce abnormal timing delays leading to systems errors, harmful in safety-critical applications. Performance Failure Prediction (PFP), instead of error detection, becomes necessary, particularly in the presence of aging effects. In this paper, an on-line BIST methodology for PFP in a standard cell design flow is proposed. The methodology is based on the detection of abnormal delays associated with critical signal paths. PVTA-resilient aging sensors are designed. Multi-level simulation is used. Functional and structural test pattern generation is performed, targeting the detection of critical path delay faults. A sensor insertion technique is proposed, together with an up-graded version of a proprietary software tool, DyDA. Finally, a novel strategy for gate-level Aging Fault injection is proposed, using the concept of an Aging de-rating factor, KA. Results are presented for a Serial Parallel Interface (SPI) controller, designed with commercial UMC 130 nm CMOS technology and Faraday™ cell library. Only seven sensors are required to monitor unsafe performance operation, due to Negative Bias Thermal Instability (NBTI)-induced aging.

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  • Bruno Jacinto, Carlos Moreira, Marcelino Santos

    This work proposes a digital implementation of the Sliding Mode Control law in a DC–DC Buck converter. The control law is implemented monitoring only the DC–DC output voltage, and is capable of producing a maximum overshoot/undershoot of 50 mV for load transients from 0 A to 1.5 A and vice versa. The maximum settling time for these conditions at 1.5 % is 5.51 us for a load transient from 1.5 A to 0.15 A. For line transients the DC–DC converter produces minimal overshoot/undershoot. Results are present for the Matlab® model with the continuous control law and for the final implementation using HSim® with the digital control law implementation. The ADC is implemented using a current controlled delay line and it is insensitive to layout parasitics, temperature, supply voltage and process parameters changes. The ADC self calibration capability is considered a major original contribution of this work. The ADC and the digital control where designed using AMS CMOS technology C35B4 (0.35 um).

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  • Nuno Dias, Marcelino Santos, Ângelo Monteiro, Pedro Braga and Alexandre Neves

    In this paper we propose an optimization method for low power, high-efficiency DC–DC conversion. A detailed analysis of a multi-mode Step-Down (or Buck) converter losses is presented, allowing the comparison of the power MOS channel conduction losses with their gate-driving losses in order to find the optimum gate-driving voltage that maximizes the converter's efficiency. It is shown that the gate-voltage controller can be simplified to a unique voltage value applied below a determined output current, while still achieving efficiencies over 90% at output currents as low as 10 mA. Simulation results of a 600 mA, 2 MHz, Buck commercial converter, implemented in a 65 nm technology are presented validating the developed models and control methodology. A low power (<20 uW) simple adaptive timing circuit is proposed to efficiently implement the gate-voltage controller with low complexity, low die area (0.007 mm2), and low quiescent current consumption (<2.4 uA).

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